Zonal Architecture latencies

Automotive E/E topologies are moving toward architectures where domain-centered and zone-centered configurations are used to consolidate the functionality of several ECUs and enable companies to reduce the size and weight of the wiring harness. In zonal routers, a combination of microcontroller and Ethernet switches can be used, however, such a design quickly leads to timing and routing problems. This is because a zonal architecture requires signals or messages to pass through several hops, whose latencies then add up. The resulting end-to-end latencies can therefore quickly exceed the limits set by the system, especially due to unpredictable fluctuations.

GuardKnox F.A.S.T.E.R. CommEngine is a single-chip solution that implements Zonal Gateway (Zone Controller) functionality and enables high-performance and cost-effective communication routing. The safe and secure design performs routing actions using hardware to allow for ultra-low latency with multi-gigabit bandwidth, addressing current automotive needs in connectivity and scalability.

The GuardKnox SOA Framework Explained
Zonal Architecture latencies

E/E Architecture is transitioning to the Zonal concept, increasing the need for low latency routing decisions (due to multi-hop routing) and in parallel supporting the increasing multi-gigabit traffic through the ring backbone.

To provide for these needs, the Backbone HPC are becoming high-performance routers that need to move traffic around the backbone with extremely low latency to allow proper operation of end-to-end processes between ECUs in different zones.

At the same time, Zonal Gateways are becoming communication bottlenecks, trying to balance cost-effective design with an ever-increasing amount of interfaces and traffic requirements in the zone.

  • Full communication routing between standard
    interfaces CAN/CAN-FD/LIN/Ethernet
  • Automotive Ethernet Support - 10Base-Ts,
    100Base-T, 100Base-T/1000Base-T
  • Standard Ethernet Support 10/100BaseTx,
  • Supports built-in L3 Ethernet switch
  • TSN Support on Ethernet interfaces
  • Supports wide spectrum of
    AUTOSAR PDU routing capabilities
  • Routing configuration from
    standard ARXML
  • Custom interfaces supported - e.g.
    digital sensor interfaces, analog sensor
    interfaces, SPI, I2C, etc. Including transfer
    of custom interfaces into PDU internally
  • Communication security and
    tamper-proofing capabilities
  • Communication verification and firewalling
  • Softcore μC support with ability
    to run control logic internally
  • Support external RAM and Flash memory
  • Support communication with external μP/μC
  • Provided as IP core, FPGA or ASIC

Reduce latency and improve security by PDU routing in HW

In microcontroller-based routers, the broad compatibility provided by the use of AUTOSAR software stacks is bought with, depending on the processor load, strongly fluctuating routing latency times of typically 100 μSec up to a few msec. In an FPGA, on the other hand, data flows through an application-specific pipeline and even complex operations, such as resolving the CAN ID to find the routing destination of an incoming message require only a few clock cycles. Parallel processing pipelines are implemented for each interface and operate independently of each other, so that routing latency times of a few μSec per hop are deterministically achievable without extensive optimization. The high performance allows additional security measures through real-time filters, such as Communication Lockdown from GuardKnox.

To implement this function, filters integrated in the FPGA can check all data packets in real time against the CAN database to determine whether signal values are valid. In addition, FPGA filters can monitor the repetition rates of certain cyclic messages, which are also specified in the CAN database, in order to detect sensor errors or possible denial-of-service (DOS) attacks. In both cases, unnecessary data traffic and processing load can be avoided by not forwarding repeated messages and optionally generating programmable status messages.


Interfaces and cores could be added or removed per demand:


Sub-Zonal CommEngine: targeted at localized aggregation of low bandwidth interfaces (CAN, LIN, sensors, I/O) into a single high bandwidth upstream interface (Ethernet) such as a sub-zonal door module.


Zonal CommEngine: targeted at Zonal GW application and used for routing between low-speed and high-speed interfaces, PDU construction and reconstruction, streaming, security and multi-gigabit switching. Additional computation cores MCU/CPU/GPU/NPU can be added or removed according to specific applications acceleration needs.


HPC Connectivity: CommEngine can be also integrated in HPC for interconnection of high-bandwidth Backbone and external Sensors, ECUs and Gateways.


  • Networking and Applications acceleration
  • Easy to integrate single chip solution
  • Cost reduction from MCU + Switch solution
  • Wiring harness reduction by enabling Zonal Architecture


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